1. Field of Invention
The present invention relates to a method of manufacturing multilevel interconnects. More particularly, the present invention relates to a method of manufacturing a via plug.
2. Description of Related Art
In the semiconductor manufacturing process, the devices are connected to each other through the metal interconnects. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent metal layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug in the semiconductor industry. The location in the metal layer used to connect to the via plug has an allowance border to make sure that the via plug can be completely located on the surface of the metal layer, in what is known as a landed via plug.
When the design rules becomes small, there is no allowance border at the location in the metal layer used to connect to the via plug to increase the integration. This is known as a borderless structure. But the borderless via plug manufacturing process is relatively difficult. When misalignment occurs, the via plug may not be completely located on the metal layer, which is called an unlanded via plug.
In order to increase the operation efficacy of the devices and decrease the resistance-capacitance time delay effect, a new orientation forms a dielectric layer with a relatively low dielectric constant between the metal layers. However, a via plug formed in the dielectric layer with a relatively low dielectric constant leads to several problems, especially when misalignment occurs.
FIGS. 1A through 1C are schematic, cross-sectional views of the conventional process for manufacturing a via plug made of dielectric material with a low dielectric constant.
As shown in FIG. 1A, an oxide layer 104 is formed on a substrate 100 including metal lines 102. In order to obtain an even surface, a dielectric material 106 with a low dielectric constant is formed to fill gaps 107 between the metal lines 102. An oxide layer 108 is deposited over the substrate 100 to form a sandwich-structure dielectric layer.
As shown in FIG. 1B, a patterned photoresist layer 110 is formed on the oxide layer 108. The oxide layer 108 is patterned to form a via hole 112 while using the patterned photoresist layer 110 as an etching mask.
As shown in FIG. 1C, the photoresist layer 110 is stripped by oxygen plasma. A cleaning process is performed to remove the remaining photoresist layer and the manufacturing process by-product by acetone solution, post-stripper rinse solution and de-ionized water. The via hole 112 is filled with metal layer 114 to finish the via plug manufacturing process.
In order to form the via holes with different depths, it is common to perform over-etching process during the formation of the via hole 112 in the oxide layer 108. However, the etching rate of the dielectric layer 106 with a low dielectric constant is larger than that of the oxide layer 108. Therefore, the via hole 112 exposes and may penetrate the dielectric material 106, even to the point of penetrating through the via hole 112 when the misalignment occurs. The Si--H bonds of the dielectric material 106 exposed by the misalignment via hole are oxidized into the Si--OH bonds in the subsequent processes of removing the photoresist layer 110 and the cleaning process. The vapor is produced from the Si--OH bonds by filling the via hole 112 with the metal layer 114 at a high temperature, so that it is difficult to till the via hole 112 with the metal layer 114 and the step coverage of the metal layer 114 in the via hole 112 is worse. Both the keyhole 116 and the poisoned via plug occur due to the formation of the vapor.